A 10-Transistor 65 nm SRAM Cell Tolerant to Single-Event Upsets

被引：7

作者：

Li, Yuanqing ^{[1
]}

Li, Lixiang ^{[2
,3
]}

Ma, Yuan ^{[2
]}

Chen, Li ^{[1
]}

Liu, Rui ^{[1
]}

Wang, Haibin ^{[1
]}

Wu, Qiong ^{[4
]}

Newton, Michael ^{[1
]}

Chen, Mo ^{[1
]}

机构：

[1] Univ Saskatchewan, Dept Elect & Comp Engn, Saskatoon, SK, Canada

[2] Dalhousie Univ, Dept Elect & Comp Engn, Halifax, NS, Canada

[3] TSMC Design Technol Canada, Kanata, ON, Canada

[4] China Univ Petr, Coll Informat & Control Engn, Qingdao, Peoples R China

来源：

JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS | 2016年 / 32卷 / 02期

基金：

加拿大自然科学与工程研究理事会;

关键词：

Alpha particle; Proton; Single event upset (SEU); Soft error rate (SER); SRAM; CMOS TECHNOLOGY; MEMORY CELL; DESIGN; LAYOUT;

D O I：

10.1007/s10836-016-5573-5

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel SRAM cell tolerant to single-event upsets (SEUs) is presented in this paper. By adding four more transistors inside, the proposed circuit can obtain higher critical charge at each internal node compared to the conventional 6-transistor (6T) cell. Arrays of 2k-bit capacitance of these two designs were implemented in a 65 nm CMOS bulk technology for comparison purpose. Radiation experiments showed that, at the nominal 1.0 V supply voltage, the proposed cell achieves 47.1 % and 49.3 % reduction in alpha and proton soft error rates (SER) with an area overhead of 37 %.

引用

页码：137 / 145

页数：9

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