Advanced Color Filter Isolation Technology for Sub-Micron Pixel of CMOS Image Sensor

被引:3
|
作者
Bak, Hojin [1 ]
Lee, Horyeong [1 ]
Kim, Won-Jin [1 ]
Choi, Inho [1 ]
Kim, Hanjun [1 ]
Kim, Dongha [1 ]
Lee, Hanseung [1 ]
Han, Sukman [1 ]
Lee, Kyoung-In [1 ]
Do, Youngwoong [1 ]
Cho, Minsu [1 ]
Baek, Moung-Seok [1 ]
Kim, Kyungdo [1 ]
Park, Wonje [1 ]
Kang, Seong-Hun [1 ]
Hong, Sung-Joo [1 ]
Oh, Hoon-Sang [1 ]
Song, Changrock [1 ]
机构
[1] SK Hynix Inc, Icheon, Gyeonggi Do, South Korea
关键词
D O I
10.1109/IEDM45625.2022.10019484
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this work, novel color filter isolation technology, which adopts air, the lowest refractive index material on the earth, as a major component of an optical grid structure for sub-micron pixels of a CMOS image sensor, is presented. Metal in a conventional metal grid structure, which has been widely used for mobile CMOS image sensors, was replaced by the air. The image quality improvement was verified through the enhanced optical performance of the air- grid-assisted pixels.
引用
收藏
页数:4
相关论文
共 50 条
  • [1] Highly Efficient Color Separation and Focusing in the Sub-micron CMOS Image Sensor
    Yun, Seokho
    Roh, Sookyoung
    Lee, Sangyun
    Park, Hongkyu
    Lim, Minwoo
    Ahn, Sungmo
    Choo, Hyuck
    [J]. 2021 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2021,
  • [2] COMBINATION OF LOCOS AND BOX ISOLATION FOR SUB-MICRON CMOS TECHNOLOGY
    HURLEY, K
    MURKIN, P
    ZELLER, C
    [J]. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1988, 135 (11) : C537 - C537
  • [4] Development of Pixel Detector in Novel Sub-micron Technology SOI CMOS 200 nm
    Bugiel, Szymon
    Dasgupta, Roma
    Glab, Sebastian
    Idzik, Marek
    Kapusta, Piotr
    [J]. 2014 PROCEEDINGS OF THE 21ST INTERNATIONAL CONFERENCE ON MIXED DESIGN OF INTEGRATED CIRCUITS & SYSTEMS (MIXDES), 2014, : 205 - 208
  • [5] Air-gap guard ring for pixel sensitivity and crosstalk improvement in deep sub-micron CMOS image sensor
    Yaung, DN
    Wuu, SG
    Chien, HC
    Hsu, TH
    Tseng, CH
    Lin, JS
    Chen, JJ
    Lo, CH
    Yu, CY
    Tsai, CS
    Wang, CS
    [J]. 2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, 2003, : 401 - 404
  • [6] A SUB-MICRON CMOS PROCESS EMPLOYING TRENCH ISOLATION
    ROBERTS, MC
    BOLBOT, PH
    FOSTER, DJ
    [J]. JOURNAL DE PHYSIQUE, 1988, 49 (C-4): : 533 - 536
  • [7] Advanced planarized passivation for sub-micron technology
    Ryu, CK
    Huang, J
    [J]. MICROELECTRONIC ENGINEERING, 1999, 45 (04) : 393 - 399
  • [8] Advanced planarized passivation for sub-micron technology
    PECVD Dielectric Film Technol. A., Planarization Dielectric D., Santa Clara, CA 94054, United States
    [J]. Microelectron Eng, 4 (393-399):
  • [9] Investigation on metal pillar defect in sub-micron CMOS technology
    You, Young Seon
    Kim, Nam Sung
    Yew, Wong Wing
    Ho, Eng Keong
    Chua, Chun Peng
    Lee, Yang Bum
    Se, Kwang Leong
    Son, Dong Ju
    Shukla, Dhruva
    Mukhopadhyay, M.
    Pey, Kin San
    [J]. ISSM 2006 CONFERENCE PROCEEDINGS- 13TH INTERNATIONAL SYMPOSIUM ON SEMICONDUCTOR MANUFACTURING, 2006, : 443 - 446
  • [10] LITHOGRAPHY FOR A SUB-MICRON CMOS PROCESS
    POPPERT, P
    NOVAK, S
    WRIGHT, P
    [J]. PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS, 1985, 538 : 46 - 50