Development of Pixel Detector in Novel Sub-micron Technology SOI CMOS 200 nm

被引:0
|
作者
Bugiel, Szymon [1 ]
Dasgupta, Roma [1 ]
Glab, Sebastian [1 ]
Idzik, Marek [1 ]
Kapusta, Piotr [2 ]
机构
[1] AGH Univ Sci & Technol, PL-30059 Krakow, Poland
[2] Inst Nucl Phys PAN, PL-31342 Krakow, Poland
关键词
Silicon-On-Insulator (SOI); SOI sensor; Double SOI; pixel detector; front-end electronic; correlated double sampling (CDS);
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents the design of a new monolithic Silicon-On-Insulator pixel sensor in 200 nm SOI CMOS technology. The main application of the proposed pixel detector is the spectroscopy, but it can also be used for the minimum ionising particle (MIP) tracking in particle physics experiments. For this reason the overriding goal of the project was to increase the signal to noise ratio of the readout circuit and sensor.
引用
收藏
页码:205 / 208
页数:4
相关论文
共 50 条
  • [1] Design and Simulations of the 10-bit SAR ADC in Novel Sub-micron Technology 200 nm SOI CMOS
    Dasgupta, Roma
    Bugiel, Szymon
    Glab, Sebastian
    Idzik, Marek
    Moron, Jakub
    Kapusta, Piotr
    [J]. 2014 PROCEEDINGS OF THE 21ST INTERNATIONAL CONFERENCE ON MIXED DESIGN OF INTEGRATED CIRCUITS & SYSTEMS (MIXDES), 2014, : 175 - 179
  • [2] Advanced Color Filter Isolation Technology for Sub-Micron Pixel of CMOS Image Sensor
    Bak, Hojin
    Lee, Horyeong
    Kim, Won-Jin
    Choi, Inho
    Kim, Hanjun
    Kim, Dongha
    Lee, Hanseung
    Han, Sukman
    Lee, Kyoung-In
    Do, Youngwoong
    Cho, Minsu
    Baek, Moung-Seok
    Kim, Kyungdo
    Park, Wonje
    Kang, Seong-Hun
    Hong, Sung-Joo
    Oh, Hoon-Sang
    Song, Changrock
    [J]. 2022 INTERNATIONAL ELECTRON DEVICES MEETING, IEDM, 2022,
  • [4] Silicon pixel detector prototyping in SOI CMOS technology
    Dasgupta, Roma
    Bugiel, Szymon
    Idzik, Marek
    Kapusta, Piotr
    Kucewicz, Wojciech
    Turala, Michal
    [J]. ELECTRON TECHNOLOGY CONFERENCE 2016, 2016, 10175
  • [5] Perspectives for Low Noise Detector Readout in a Sub-quarter-micron CMOS SOI Technology
    Re, Valerio
    Gaioni, Luigi
    Manghisoni, Massimo
    Ratti, Lodovico
    Speziali, Valeria
    Traversi, Gianluca
    Yarema, Ray
    [J]. 2007 IEEE NUCLEAR SCIENCE SYMPOSIUM CONFERENCE RECORD, VOLS 1-11, 2007, : 1873 - +
  • [6] Scaling SOI photonics to micron and sub-micron devices
    Dainesi, P
    Moselund, K
    Mazza, M
    Thévenaz, L
    Ionescu, A
    [J]. Opto-Ireland 2005: Nanotechnology and Nanophotonics, 2005, 5824 : 13 - 22
  • [7] Investigation on metal pillar defect in sub-micron CMOS technology
    You, Young Seon
    Kim, Nam Sung
    Yew, Wong Wing
    Ho, Eng Keong
    Chua, Chun Peng
    Lee, Yang Bum
    Se, Kwang Leong
    Son, Dong Ju
    Shukla, Dhruva
    Mukhopadhyay, M.
    Pey, Kin San
    [J]. ISSM 2006 CONFERENCE PROCEEDINGS- 13TH INTERNATIONAL SYMPOSIUM ON SEMICONDUCTOR MANUFACTURING, 2006, : 443 - 446
  • [8] COMBINATION OF LOCOS AND BOX ISOLATION FOR SUB-MICRON CMOS TECHNOLOGY
    HURLEY, K
    MURKIN, P
    ZELLER, C
    [J]. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1988, 135 (11) : C537 - C537
  • [9] Accurate timing modeling and design-kit development for a sub-micron CMOS technology
    Torki, K
    Saulnier, S
    [J]. MICROELECTRONICS EDUCATION, 1998, : 239 - 242
  • [10] Electrical characterization by sub-micron probing technique on 90nm CMOS technology for failure analysis
    Giret, C
    Faure, D
    [J]. IPFA 2004: PROCEEDINGS OF THE 11TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS, 2004, : 271 - 274