A fast-lock low-power all-digital DLL-based clock generator with fractional multiple technique

In this paper, a fast-lock low-power all-digital delay-locked-loop (ADDLL)-based clock generator is proposed that generates fractional multiples of a reference frequency. The proposed clock generator comprises an ADDLL with dual-loop architecture and a fractional frequency multiplier. The coarse tune loop and fine tune loop of the proposed ADDLL can achieve a fast locking time and decrease the static phase error. Moreover, the proposed frequency multiplier can synthesize the 28-phase output clocks of the ADDLL to achieve high multiples. The experimental results demonstrated that the output frequency range of the proposed clock generator was between 176 and 224 MHz, with multiplication factors of 11 x, 11.5 x, 12 x, 12.5 x, 13 x, 13.5 x, and 14 x to cover the very high frequency (VHF) frequency band, where every channel had a bandwidth of 8 MHz. Moreover, the output duty cycle was close to 50% because a divider was used to generate the output signal and the lock time was less than 20 clock cycles. The clock generator was fabricated using a 0.18-mu m standard CMOS process, with an active area of 0.59 mm(2), power dissipation of 6.7 mW at 224 MHz, and phase noise of - 94.33 dBc/Hz with an offset of 1 MHz. Furthermore, at 176 MHz, the root-mean-square jitter was 25.01 ps, which was less than 0.45% of the output period.