A 0.9V 2.72μW 200 kS/s SAR ADC with ladder-based time-domain comparator

被引：2

作者：

Yang, Xiaolin ^{[1
]}

Zhou, Yin ^{[1
]}

Tang, Lihan ^{[1
]}

Dong, Yangtao ^{[1
]}

Zhao, Menglian ^{[1
]}

Deng, Lin ^{[1
]}

Wu, Xiaobo ^{[1
]}

Zhu, Xiaolei ^{[1
]}

机构：

[1] Zhejiang Univ, Inst VLSI Design, 38 Rd Zheda, Hangzhou, Zhejiang, Peoples R China

来源：

IEICE ELECTRONICS EXPRESS | 2017年 / 14卷 / 05期

基金：

中国国家自然科学基金;

关键词：

bio-medical devices; SAR ADC; time-domain comparator;

D O I：

10.1587/elex.14.20170003

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a 200 kS/s 12-bit successive approximation ADC with a new ladder-based time-domain comparator. The proposed comparator utilizes differential multi-ladder stages, resulting in improvement of gain and noise performance. The chip is designed and fabricated in a standard 0.18 mu m CMOS technology with area of 0.127mm(2). With a supply of 0.9V, the ADC consumes 2.72 mu W at the sampling rate of 200 kS/s. The measured SNDR and SFDR are 61.6 dB and 66.1 dB respectively, providing an ENOB of 9.9 bits, and the corresponding FOM of 28 fJ/conv-step.

引用

页数：9

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