A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface

被引：126

作者：

Lee, Seon-Kyoo ^{[1
]}

Park, Seung-Jin ^{[1
]}

Park, Hong-June ^{[1
]}

Sim, Jae-Yoon ^{[1
]}

机构：

[1] Pohang Univ Sci & Technol POSTECH, Dept Elect & Elect Engn, Pohang 790784, Kyungbuk, South Korea

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2011年 / 46卷 / 03期

基金：

新加坡国家研究基金会;

关键词：

Analog-to-digital converter; comparator; successive approximation ADC; sensor interface; SAR ADC; CMOS;

D O I：

10.1109/JSSC.2010.2102590

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a 100 kS/s, 1.3 mu W, 9.3 ENOB successive approximation ADC with a time-domain comparator. The proposed time-domain comparator utilizes a differential multi-stage VCDL, resulting in a highly digital operation eliminating static power consumption. The effects of gain, noise, and offset are also investigated by detailed analysis which proves the feature of reducing the input-referred noise and offset by simply increasing the number of delay stages. For verification, the proposed ADC is fabricated in a 0.18 mu m CMOS. With a single supply voltage of 0.6 V, the ADC consumes 1.3 mu W at the maximum sampling rate of 100 kS/s. The measured ENOB is 9.3 b showing a figure of merit of 21 fJ/conversion-step.

引用

页码：651 / 659

页数：9

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