A Hardware-Efficient Deblocking Filter Design for HEVC

被引：0

作者：

Fang, Chih-Chung ^{[1
]}

Chen, I-Wen ^{[1
]}

Chang, Tian-Sheuan ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Inst Elect, Hsinchu 30050, Taiwan

来源：

2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2015年

关键词：

Deblocking filter; HEVC; VLSI architecture design;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a hardware-efficient deblocking filter architecture for High Efficiency Video Coding (HEVC) to reduce visual artifacts at block boundaries. This design proposes an interleaved scheduling to reduce the intermediate data storage to be 1536 bits instead of whole 8192 bits. The implementation with 90 nm CMOS technology can support real-time deblocking operation of 7682x4320@30 fps under 141.5 MHz with only 31K gate count.

引用

页码：1786 / 1789

页数：4

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