Asymmetrical Multilevel Inverter Topology

Multilevel inverters (MLIs) are being extensively used in high voltage/power applications due to their superior features like lesser dv/dt stress on switches and less harmonic distortion over two level inverters. However for higher number of levels, there is a considerable increase of number of power switches, voltage stress and dc voltage sources. The increased device count directly affects the cost of the inverter and also makes the system complex. In order to improve the output voltage levels, an MLI topology is proposed in this paper with less device count. The proposed topology can generate 7-level and 11-level output voltage in asymmetric source configuration with a single cell, by using multi carrier pulse width modulation (MC-PWM) technique. Further, the superior characteristics of the proposed topology have been proved by comparing with the recent literature. The robustness and vulnerability of the proposed topology has been verified through simulation analysis under different operating conditions.