A Shared-Way Set Associative architecture for on-chip caches

The scheme described in this paper is an alternative cache memory organization called "Shared-Way Set Associative" (SWSA). It consists of a modified two-way set associative scheme in which one bank is larger than the other. We show how better use of memory is obtained, without the costs that higher-associativities have. An expression for calculating the non-integer degree of associativity of SWSA caches is given. Several replacement policies are discussed. Miss rate statistics for the SPEC95 benchmarks are presented for first and second level SWSA caches, together with a detailed analysis of conflicts using the D3C classification of misses. For large caches the miss rates of SWSA caches are similar to those of 33% larger two-way caches. The issue of access time is addressed, and we explain why SWSA caches may have advantages, specially for configurations with very unbalanced banks which have miss rates that are very similar to those of slightly smaller two-way caches.