A fast and accurate delay dependent method for switching estimation of large combinational circuits

被引:2
|
作者
Theoharis, S
Theodoridis, G
Soudris, D [1 ]
Goutis, C
Thanailakis, A
机构
[1] Democritus Univ Thrace, Dept Elect & Comp Engn, VLSI Design & Testing Ctr, GR-67100 Xanthi, Greece
[2] Univ Patras, Dept Elect & Comp Engn, VLSI Design & Testing Ctr, Rion 26110, Greece
[3] ALMA Technol, Pikermi Attika 19009, Greece
关键词
gate level; power estimation; CMOS circuit; low power design; computer aided design;
D O I
10.1016/S1383-7621(02)00120-0
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Assuming inertial gate delay model, the first-order temporal correlation and the structural dependencies, a probabilistic method to estimate the switching activity of a combinational circuit, is introduced. To capture the first temporal correlation a novel mathematical model and the associated new formulas are derived. Also, a modified boolean function, which describes the logic and timing behavior of each signal, is introduced. To capture the structural dependencies an efficient new method to partition a large circuit into small independent sub-circuits is proposed. Finally, an algorithm that evaluates the switching activity of any circuit node is presented. (C) 2002 Elsevier Science B.V. All rights reserved.
引用
下载
收藏
页码:113 / 124
页数:12
相关论文
共 50 条
  • [1] Past delay-dependent power estimation of large combinational circuits
    Jou, JM
    Chen, SC
    Wang, CL
    ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6, 1998, : E53 - E56
  • [2] Statistical estimation of delay-dependent switching activities in embedded CMOS combinational circuits
    Lim, YJ
    Soma, M
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1997, 5 (03) : 309 - 319
  • [3] A statistical approach to the estimation of delay-dependent switching activities in CMOS combinational circuits
    Lim, YJ
    Son, KI
    Park, HJ
    Soma, M
    33RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 1996, 1996, : 445 - 450
  • [4] An accurate and fast reliability analysis method for combinational circuits
    Zandevakili, Hamed
    Mahani, Ali
    Saneei, Mohsen
    COMPEL-THE INTERNATIONAL JOURNAL FOR COMPUTATION AND MATHEMATICS IN ELECTRICAL AND ELECTRONIC ENGINEERING, 2015, 34 (03) : 979 - 995
  • [5] Fast and Accurate SER Estimation for Large Combinational Blocks in Early Stages of the Design
    Anglada, Marti
    Canal, Ramon
    Aragon, Juan L.
    Gonzalez, Antonio
    IEEE TRANSACTIONS ON SUSTAINABLE COMPUTING, 2021, 6 (03): : 427 - 440
  • [6] Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model
    Fadl, Omnia S.
    Abu-Elyazeed, Mohamed F.
    Abdelhalim, Mohamed B.
    Amer, Hassanein H.
    Madian, Ahmed H.
    JOURNAL OF ADVANCED RESEARCH, 2016, 7 (01) : 89 - 94
  • [7] A fast and accurate delay estimation method for buffered interconnects
    Gao, YX
    Wong, DF
    PROCEEDINGS OF THE ASP-DAC 2001: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2001, 2001, : 533 - 538
  • [8] Functional complexity estimation for large combinational circuits
    Aborhey, S
    IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 2002, 149 (02): : 39 - 45
  • [9] Discrete-state analysis technique for accurate estimation of switching activities in embedded CMOS combinational circuits
    Lim, YJ
    Soma, M
    ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE, 1997, : 1800 - 1803
  • [10] An Efficient SER Estimation Method for Combinational Circuits
    Kehl, Natalja
    Rosenstiel, Wolfgang
    IEEE TRANSACTIONS ON RELIABILITY, 2011, 60 (04) : 742 - 747