Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model

被引：3

作者：

Fadl, Omnia S. ^{[1
]}

Abu-Elyazeed, Mohamed F. ^{[1
]}

Abdelhalim, Mohamed B. ^{[2
]}

Amer, Hassanein H. ^{[3
]}

Madian, Ahmed H. ^{[4
]}

机构：

[1] Cairo Univ, Fac Engn, Elect & Commun Dept, Univ St,POB 268, Giza 12316, Egypt

[2] AASTMT, CCIT, POB 2033,El Moshir Ismail St, Cairo, Egypt

[3] Amer Univ Cairo, Elect & Commun Engn Dept, POB 74, New Cairo 11835, Egypt

[4] NCRRT, Radiat Engn Dept, 3 Ahmed El Zomor St,POB 29, Cairo 11787, Egypt

来源：

JOURNAL OF ADVANCED RESEARCH | 2016年 / 7卷 / 01期

关键词：

CMOS combinational logic circuits; Logic pictures; Real-delay model; Switching activity; Dynamic power estimation; Toggle rate;

D O I：

10.1016/j.jare.2015.02.006

中图分类号：

O [数理科学和化学]; P [天文学、地球科学]; Q [生物科学]; N [自然科学总论];

学科分类号：

07 ; 0710 ; 09 ;

摘要：

Dynamic power estimation is essential in designing VLSI circuits where many parameters are involved but the only circuit parameter that is related to the circuit operation is the nodes' toggle rate. This paper discusses a deterministic and fast method to estimate the dynamic power consumption for CMOS combinational logic circuits using gate-level descriptions based on the Logic Pictures concept to obtain the circuit nodes' toggle rate. The delay model for the logic gates is the real-delay model. To validate the results, the method is applied to several circuits and compared against exhaustive, as well as Monte Carlo, simulations. The proposed technique was shown to save up to 96% processing time compared to exhaustive simulation. (C) 2015 Production and hosting by Elsevier B.V. on behalf of Cairo University.

引用

页码：89 / 94

页数：6