Analysis of parasitic effects for pin diode SPDT switch

被引：2
|
作者：
Sun, P. [1 ]
Heo, D. [2 ]
机构：
[1] IBM Corp, Essex Jct, VT 05452 USA
[2] Washington State Univ, Sch Elect Engn & Comp Sci, Pullman, WA 99163 USA
来源：
ELECTRONICS LETTERS | 2009年 / 45卷 / 10期
关键词：
CMOS;
D O I：
10.1049/el.2009.0691
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A comparison of insertion loss between a conventional clockwise and a proposed counter-clockwise SiGe pin diode SPDT switch based on an analysis of parasitic effects is presented. In a silicon-based process, the counter-clockwise switch is analytically demonstrated to have lower insertion loss than the clockwise switch owing to the alleviation of parasitic effects. Measurement data show good agreement with the presented analysis.
引用
收藏
页码：503 / U32
页数：2
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