Demonstration of Low Cost TSV Fabrication in Thick Silicon Wafers

被引：0

作者：

Vick, E. ^{[1
]}

Temple, D. S. ^{[1
]}

Anderson, R. ^{[1
]}

Lannon, J. ^{[1
]}

Li, C. ^{[2
]}

Peterson, K. ^{[2
]}

Skidmore, G. ^{[2
]}

Han, C. J. ^{[2
]}

机构：

[1] RTI Int, Res Triangle Pk, NC 27709 USA

[2] DRS RSTA Inc, Dallas, TX USA

来源：

2014 IEEE 64TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) | 2014年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Low cost wafer-level chip-scale vacuum packaging (WLCSVP) imposes unique constraints on potential implementation of through-silicon vias (TSVs). A WLCSVP requires a relatively thick substrate to prevent mechanical failure. Two approaches for integrating TSVs in thick silicon wafers have been successfully demonstrated. Both approaches enable TSV formation from the backside of a device wafer and are compatible with the requirements of subsequent packaging operations. We achieved low contact resistance between TSVs and frontside Ti/Cu and Al metallization, while demonstrating high isolation resistance and high TSV yield.

引用

页码：1641 / 1647

页数：7

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