On the topography simulation of memory cell trenches for semiconductor manufacturing deposition processes using the level set method

Etching and deposition of Silicon trenches is an important semiconductor manufacturing step for state of the art memory cells and other semiconductor devices like, e.g., Power MOSFETS. Understanding and simulating the transport of gas species and surface evolution enables to achieve void-less filling of deep trenches, to predict the resulting profiles, and thus to optimize the process parameters with respect to manufacturing throughput and the resulting memory cells. An accurate and fast method for surface evolution has been combined with the simulation of the transport of gas species above the wafer surface and applied to a SiO2 deposition process, In experiments a SiO2 layer was deposited into trenches roughly 4mum deep and 2mum wide, where the final layer thickness was in the range of 1 mum for the flat wafer surface. Simulation results are discussed and compared to scanning electron microscope pictures, where all effects were reproduced in the simulation and good quantitative agreement was achieved as well.