Composite step-graded collector of InP/InGaAs/InP DHBT for minimised carrier blocking

被引：20
|
作者：
Chor, EF
Peng, CJ
机构：
[1] National University of Singapore, Department of Electrical Engineering, Centre for Optoelectronics, Singapore 0511
来源：
ELECTRONICS LETTERS | 1996年 / 32卷 / 15期
关键词：
heterojunction bipolar transistors; semiconductor devices;
D O I：
10.1049/el:19960889
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A composite step-graded collector of InP/InGaAs/InP DHBT has been investigated for minimised carrier blocking. The optimised collector has the following sub-layers: a 100 Angstrom n InGaAs layer; three 200 Angstrom n InGaAsP layers; and a 100 Angstrom, n = 3 x 10(17) cm(-3) InP layer, and the rest are n InP. The InGaAsP layers should be chosen to give approximately equal band offset at the heterointerfaces.
引用
收藏
页码：1409 / 1410
页数：2
相关论文
共 50 条
  • [41] Submicrometer InP/InGaAs DHBT Architecture Enhancements Targeting Reliability Improvements
    Kone, Gilles A.
    Grandchamp, Brice
    Hainaut, Cyril
    Marc, Francois
    Labat, Nathalie
    Zimmer, Thomas
    Nodjiadjim, Virginie
    Riet, Muriel
    Dupuy, Jean-Yves
    Godin, Jean
    Maneux, Cristell
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2013, 60 (03) : 1068 - 1074
  • [42] Optimization of InGaAs/InP DHBT devices for use in high speed circuits
    Kopf, RF
    Wang, YC
    Hamm, RA
    Ryan, RW
    Tate, A
    Melendes, MA
    Pullela, R
    Georgiou, G
    Mattia, JP
    Baeyens, Y
    Tsai, HS
    Chen, YK
    STATE-OF-THE-ART PROGRAM ON COMPOUND SEMICONDUCTORS (SOTAPOCS XXXI), 1999, 99 (17): : 169 - 176
  • [43] 3.21 ps ECL gate using InP/InGaAs DHBT technology
    Ishii, K
    Nosaka, H
    Ida, M
    Kurishima, K
    Shibata, T
    ELECTRONICS LETTERS, 2003, 39 (20) : 1434 - 1436
  • [44] Reliability of submicron InGaAs/InP DHBT under thermal and electrical stresses
    Kone, G. A.
    Grandchamp, B.
    Hainaut, C.
    Marc, F.
    Maneux, C.
    Labat, N.
    Zimmer, T.
    Nodjiadjim, V.
    Riet, M.
    Godin, J.
    MICROELECTRONICS RELIABILITY, 2011, 51 (9-11) : 1730 - 1735
  • [45] Preliminary results of storage accelerated aging test on InP/InGaAs DHBT
    Kone, G. A.
    Grandchamp, B.
    Hainaut, C.
    Marc, F.
    Maneux, C.
    Labat, N.
    Zimmer, T.
    Nodjiadjim, V.
    Godin, J.
    MICROELECTRONICS RELIABILITY, 2010, 50 (9-11) : 1548 - 1553
  • [46] High-performance composite-collector InP/InGaAs heterojunction bipolar transistors
    Kurishima, K
    Ida, M
    Ishii, K
    Watanabe, N
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2004, 43 (4B): : 2243 - 2249
  • [47] Breakdown characteristics of InP/InGaAs composite-collector double heterojunction bipolar transistor
    Lin, YS
    APPLIED PHYSICS LETTERS, 2003, 83 (26) : 5545 - 5547
  • [48] PICOSECOND CARRIER DYNAMICS IN HIGHLY EXCITED INGAAS/INP/INGAASP/INP STRUCTURES
    PETRAUSKAS, M
    JUODKAZIS, S
    NETIKIS, V
    WILLANDER, M
    OUACHA, A
    HAMMARLUND, B
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 1992, 7 (11) : 1355 - 1358
  • [49] Temperature dependence of avalanche multiplication in InP-based HBTs with InGaAs/InP composite collector: Device characterization and physics model
    Wang, H
    Yang, H
    Neo, WP
    Radhakrishnan, K
    Tan, CL
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (12) : 2335 - 2343
  • [50] Improved quality of InP layer on GaAs substrates by using compositionally modulated step-graded AlGaInAs buffers
    He, Yang
    Yan, Wei
    Sun, Yurun
    Dong, Jianrong
    JOURNAL OF MATERIALS SCIENCE-MATERIALS IN ELECTRONICS, 2019, 30 (17) : 16251 - 16256
12345