Energy Optimization of LDPC Decoder Circuits with Timing Violations

被引：0

作者：

Leduc-Primeau, Francois ^{[1
]}

Kschischang, Frank R. ^{[2
]}

Gross, Warren J. ^{[1
]}

机构：

[1] McGill Univ, Dept Elect & Comp Engn, Montreal, PQ, Canada

[2] Univ Toronto, Dept Elect & Comp Engn, Toronto, ON, Canada

来源：

2015 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS (ICC) | 2015年

关键词：

DESIGN;

D O I：

暂无

中图分类号：

TN [电子技术、通信技术];

学科分类号：

0809 ;

摘要：

This paper presents a quasi-synchronous design approach for signal processing circuits, in which timing violations are permitted, but without the need for a hardware compensation mechanism. A quasi-synchronous low-density parity-check decoder processing circuit based on the offset min-sum algorithm is designed, achieving the same performance and occupying the same area as a conventional synchronous circuit, but using up to 28% less energy.

引用

页码：412 / 417

页数：6

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