Sequential circuit test generation for IDDQ testing of bridging faults

被引：7
|
作者：
Higami, Y
Maeda, T
Kinoshita, K
机构：
来源：
IEEE INTERNATIONAL WORKSHOP ON IDDQ TESTING, DIGEST OF PAPERS | 1997年
关键词：
D O I：
10.1109/IDDQ.1997.633006
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a test generation method for sequential circuits assuming IDDQ testing. We consider external bridging faults and internal bridging faults as a target fault, Tt ss generation for external bridging faults consists of three phases as 1) use of weighted random vectors, 2) set of target values an selected signal lines, 3) deterministic test generation for undetected faults. In order to detect internal bridging faults, we use a sequential test generator for stuck-at faults. Finally experimental results for ISCAS'89 benchmark circuits are given.
引用
收藏
页码：12 / 16
页数：5
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