SoC leakage power reduction algorithm by input vector control

被引:0
|
作者
Chang, Xiaotao [1 ]
Fan, Dongrui [1 ]
Han, Yinhe [1 ]
Zhang, Zhimin [1 ]
机构
[1] Chinese Acad Sci, Inst Comp Technol, Beijing 100080, Peoples R China
关键词
leakage power; input vector control; low power design; gate-level simulator; SoC;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Input vector control is an effective method to reduce leakage power when a circuit enters sleep mode. It seeks to find a vector that minimizes leakage power to be statically applied to the primary inputs of a circuit. This paper presents a fast algorithm to search the input vector which can lead to the minimal leakage power. In order to accelerate the evaluation procedure, the circuit under simulation is reduced by circuit partition based on the signal probability model first. Then, a searching algorithm based on sub-circuit is used to find the target input vector. Experimental results on large combinational circuits of ISCAS85 benchmark and a real general-purpose SoC show this algorithm can accelerate calculation over three times with acceptable accuracy (error about 0.14%).
引用
收藏
页码:86 / 89
页数:4
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