SoC leakage power reduction algorithm by input vector control

被引:0
|
作者
Chang, Xiaotao [1 ]
Fan, Dongrui [1 ]
Han, Yinhe [1 ]
Zhang, Zhimin [1 ]
机构
[1] Chinese Acad Sci, Inst Comp Technol, Beijing 100080, Peoples R China
关键词
leakage power; input vector control; low power design; gate-level simulator; SoC;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Input vector control is an effective method to reduce leakage power when a circuit enters sleep mode. It seeks to find a vector that minimizes leakage power to be statically applied to the primary inputs of a circuit. This paper presents a fast algorithm to search the input vector which can lead to the minimal leakage power. In order to accelerate the evaluation procedure, the circuit under simulation is reduced by circuit partition based on the signal probability model first. Then, a searching algorithm based on sub-circuit is used to find the target input vector. Experimental results on large combinational circuits of ISCAS85 benchmark and a real general-purpose SoC show this algorithm can accelerate calculation over three times with acceptable accuracy (error about 0.14%).
引用
收藏
页码:86 / 89
页数:4
相关论文
共 50 条
  • [21] Vector Control of Cycloconverter with Increased Input Power Factor
    Sarakhanova, Regina Yu
    Kharitonov, Sergey A.
    Dubkov, Ilya S.
    2014 15TH INTERNATIONAL CONFERENCE OF YOUNG SPECIALISTS ON MICRO/NANOTECHNOLOGIES AND ELECTRON DEVICES (EDM), 2014, : 429 - 432
  • [22] Interval Arithmetic Based Input Vector Control for RTL Subthreshold Leakage Minimization
    Pendyala, Shilpa
    Katkoori, Srinivas
    2012 IEEE/IFIP 20TH INTERNATIONAL CONFERENCE ON VLSI AND SYSTEM-ON-CHIP (VLSI-SOC), 2012, : 141 - 146
  • [23] IVATS: A Leakage Reduction Technique Based on Input Vector Analysis and Transistor Stacking in CMOS Circuits
    Deng, Lishuo
    Li, Keran
    Shan, Weiwei
    2023 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS, 2023,
  • [24] Particle Swarm Optimization Algorithm for Leakage Power Reduction in VLSI Circuits
    Rani, V. Leela
    Latha, M. Madhavi
    INTERNATIONAL JOURNAL OF ELECTRONICS AND TELECOMMUNICATIONS, 2016, 62 (02) : 179 - 186
  • [25] Transition Analysis for Power Reduction in SoC
    Saravanan, S.
    Silambamuthan, R.
    Balasubramaniyan, A.
    Pannerselvam, R.
    Ganesh, B.
    Selvakumar, P.
    INTERNATIONAL CONFERENCE ON MODELLING OPTIMIZATION AND COMPUTING, 2012, 38 : 655 - 660
  • [26] A Simultaneous Input Vector Control and Circuit Modification Technique to Reduce Leakage with Zero Delay Penalty
    Jayakumar, Nikhil
    Khatri, Sunil P.
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2010, 16 (01)
  • [27] Input vector control for post-silicon leakage current minimization in the presence of manufacturing variability
    Alkabani, Yousra
    Massey, Tammara
    Koushanfar, Farinaz
    Potkonjak, Miodrag
    2008 45TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2008, : 606 - +
  • [28] LEakage Control TRAnsistor (LECTRA): A novel Approach for Leakage Reduction in Low Power VLSI Design
    Kassa, Sankit R.
    Nagaria, R. K.
    JOURNAL OF ACTIVE AND PASSIVE ELECTRONIC DEVICES, 2016, 11 (01): : 53 - 77
  • [29] Compilers for leakage power reduction
    You, YP
    Lee, C
    Lee, JK
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2006, 11 (01) : 147 - 164
  • [30] Leakage Power Profiling and Leakage Power Reduction using DFT Hardware
    Sethuram, Rajamani
    Arabi, Karim
    Abu-Rahma, Mohamed
    2011 IEEE 29TH VLSI TEST SYMPOSIUM (VTS), 2011, : 46 - 51