An alternative process architecture for CMOS based high side RESURF LDMOS transistors

被引：0
|
作者：
Holland, P. M. [1 ]
Igic, P. M. [1 ]
机构：
[1] Univ Coll Swansea, Elect Syst Design Ctr, Singleton Pk, Swansea SA2 8PP, W Glam, Wales
来源：
2006 25TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, VOLS 1 AND 2, PROCEEDINGS | 2006年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An alternative CMOS manufacturing process architecture for implementing Power Integrated Circuits that may be used for applications requiring a bridge topology is presented. A RESURF N-LDMOS High-Side compatible power transistor was designed onto the new process using TSuprem4 and Medici TCAD software. Masks were designed using Cadence Virtuoso and the new structure was manufactured at X-Fab UK Ltd. The physical results show good transistor characteristics compatible for high-side applications. The Specific RDSon for the new device is 260m Omega.mm(2) and breakdown voltage for both high-side and low-side operation exceeds 100V.
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页码：207 / +
页数：3
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