A Low-Power VLSI architecture for Intra and Inter prediction in H.264

The H.264 video coding standard can achieve considerably higher coding efficiency than previous standards. The keys to this high code efficiency are mainly the two prediction modes (Intra & Inter) provided by the standard. Unfortunately these come at a cost in considerable increased complexity at the encoder. Therefore it is of high importance to design architectures that minimize the cost of the prediction modes. One computational element that is met in both, Inter and Intra Prediction modes, is that of the Sum of Absolute Differences (SAD). In this paper we present a new algorithm that can replace SAD in the two main Prediction Modes, and which can provide a more efficient hardware implementation.