Impact of Dynamic Partial Reconfiguration on CONNECT Network-on-Chip for FPGAs

被引：0
|
作者：
Ahmed, Ramy [1 ,2 ]
Mostafa, Hassan [2 ,3 ,4 ]
Khalil, A. H. [2 ]
机构：
[1] Mentor, Cairo, Egypt
[2] Cairo Univ, Elect & Commun Engn Dept, Giza 12613, Egypt
[3] Amer Univ Cairo, Ctr Nanoelect & Devices, Cairo, Egypt
[4] Zewail City Sci & Technol, Cairo, Egypt
来源：
2018 13TH INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA (DTIS 2018) | 2018年
关键词：
Dynamic Partial Reconfiguration; Network on Chip; Field Programmable Gate Arrays;
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
This work presents the Dynamic Partial Reconfiguration (DPR) support to CONNECT Network-on-Chip (NoC) and studies its impact on the network performance. Runtime reconfigurability expands the flexibility of NoCs and allows a full customization for the dynamic reconfigurable applications. In comparison with the fixed NoCs, the runtime reconfigurable NoCs result in area optimization by reusing a part of the network when idle during the runtime. A reconfiguration tool is developed which analyzes the user benchmarks in order to find the optimal network structure (configuration) for every benchmark.
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页数：5
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