A Novel Fault-Tolerant Router Architecture for Network-on-Chip Reconfiguration

In Network-on-Chip (NoC) architectures, a faulty router can isolate a functional processing element (PE) from other nodes, severely restricting the performance of the system. This paper presents a fault-tolerant router architecture that can avoid PE isolation even if the router fails. In this design, we connect the local port of the router with one of the other four ports through a fault tolerant control unit that works with the fault detection signal. If the router fails, the control unit will turn on and connect the PE with the neighboring router directly, thus protecting the system functioning. A revised XY-Routing algorithm is also presented to achieve the NoC reconfiguration when router fails. Theoretical analysis show that for a 10*10 mesh NoC, the reliability at year 10 is 20 times better than NoC implemented with traditional router. Also our design has greatly improved value for mean time to failure (MTTF). In video and DSP applications, simulation results show better power control with faulty PEs. The new architecture also has other advantages over annealing re-mapping algorithm. Our design has only 12% area overhead, which is significantly better than other approaches to deal with faults.