BIST for network-on-chip interconnect infrastructures

被引：40
|
作者：
Grecu, Cristian [1 ]
Pande, Partha [2 ]
Ivanov, Andre [1 ]
Saleh, Res [1 ]
机构：
[1] Univ British Columbia, Dept Elect & Comp Engn, SoC Res Lab, 2356 Main Mall, Vancouver, BC V6T 1Z4, Canada
[2] Washington State Univ, Sch Elect Engn & Comp Sci, Pullman, WA 99164 USA
来源：
24TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 2006年
关键词：
built-in self-test; network-on-chip; interconnect; infrastructure; unicast test; multicast test;
D O I：
10.1109/VTS.2006.22
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we present a novel built-in self-test methodology for testing the inter-switch links of network-on-chip (NoC) based chips. This methodology uses a high-level fault model that accounts for crosstalk effects due to inter-wire coupling. The novelty of our approach lies in the progressive reuse of the NoC infrastructure to transport test data to its own components under test in a bootstrap manner, and in extensively exploiting the inherent parallelism of the data transport mechanism to reduce the test time and implicitly the test cost.
引用
收藏
页码：30 / +
页数：2
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