A Strategy for Interconnect Testing in Stacked Mesh Network-on-Chip

被引：0
|
作者：
Chan, Min-Ju [1 ]
Hsu, Chun-Lung [1 ]
机构：
[1] Natl Dong Hwa Univ, Dept Elect Engn, 1,Sec 2, Da Hsueh Rd, Hualien 974, Taiwan
来源：
2010 IEEE 25TH INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS (DFT 2010) | 2010年
关键词：
built-in self-test (BIST); interconnect testing; network-on-chip (NoC);
D O I：
10.1109/DFT.2010.21
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
3D IC process has be a tendency in recent years. But the progress of IC process technologies recently has the related problems. In the 3D NoC architecture, the 3D IC process makes the placement and routing to become more complex. Then, the faults increase because of the more complex architecture. Therefore, we have to study a methodology to solve the problem. At present, the testing approach for NoC interconnect fault is based on the 2D architecture. The 3D simulated tool is not perfect. Therefore, we have to study a feasible method to test 3D architecture. In this paper, we consider how will apply a mature interconnect test approach for the 2D NoC architecture to test the 3D NoC architecture. Then, we are able to achieve the objective for increasing the yield of product through the replacement of defective chips.
引用
收藏
页码：122 / 128
页数：7
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