Static divided word matching line for low-power content addressable memory design

被引:0
|
作者
Cheng, KH
Wei, CH
Jiang, SY
机构
关键词
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
In this paper, a novel Content Addressable Memory (CAM) word structure with divided word matching line for low-power application is proposed. To reduce the comparison power consumption, the proposed CAM word structure adopts static circuit design to improve the overall system reliability and reduce the power consumption. In addition, a new CAM cell with single bit line circuit design is proposed. The single bit line design requires only one heavy loading bit line, and prevents the frequently switching that designed in conventional basic CAM cell. Based on TSMC 0.25 mum CMOS process with 2.5 V supply voltage, a 128 words by 32 bits CAM is designed. The simulation result shows that the power consumption of the proposed CAM is 17.12 mW under 300 MHz operation frequency.
引用
收藏
页码:629 / 632
页数:4
相关论文
共 50 条
  • [31] Low-power high-performance NAND match line content addressable memories
    Chaudhary, Vikas
    Clark, Lawrence T.
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2006, 14 (08) : 895 - 905
  • [32] Match line sense amplifiers with positive feedback for low-power content addressable memories
    Mohan, N.
    Fung, W.
    Wright, D.
    Sachdev, M.
    PROCEEDINGS OF THE IEEE 2006 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2006, : 297 - 300
  • [33] Design for low-power, low-cost, and high-reliability precomputation-based content-addressable memory
    Lin, CS
    Chang, JC
    Liu, BD
    APCCAS 2002: ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS, 2002, : 319 - 324
  • [34] Low power design of precomputation-based content-addressable memory
    Ruan, Shanq-Jang
    Wu, Chi-Yu
    Hsieh, Jui-Yuan
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2008, 16 (03) : 331 - 335
  • [35] A variable word-width content addressable memory for fast string matching
    Nilsen, G
    Torresen, J
    Soråsen, O
    22ND NORCHIP CONFERENCE, PROCEEDINGS, 2004, : 214 - 217
  • [36] A Low-Power Ternary Content-Addressable Memory Using Pulse Current Based Match-Line Sense Amplifiers
    Chang, Meng-Chou
    Tsai, Shih-Ju
    2013 IEEE 10TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2013,
  • [37] A Low-Power Ternary Content Addressable Memory (TCAM) With Segmented And Non-Segmented Matchlines
    Sultan, M.
    Siddiqui, M.
    Sonika
    Visweswaran, G. S.
    2008 IEEE REGION 10 CONFERENCE: TENCON 2008, VOLS 1-4, 2008, : 2302 - 2306
  • [38] Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks
    Jarollahi, Hooman
    Gripon, Vincent
    Onizawa, Naoya
    Gross, Warren J.
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 23 (04) : 642 - 653
  • [39] A Low-Power Content-Addressable Memory (CAM) using Pipe lined Search Scheme
    Song, Yibo
    Yao, Zheng
    Xiong, Xingguo
    TECHNOLOGICAL DEVELOPMENTS IN NETWORKING, EDUCATION AND AUTOMATION, 2010, : 405 - 410
  • [40] Low-power priority encoder and multiple match detection circuit for ternary content addressable memory
    Mohan, Nitin
    Fung, Wilson
    Sachdev, Manoj
    IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2006, : 253 - +