High-speed low-power adder with a new logic style: Pseudo dynamic logic (SDL)

被引：0

作者：

Chaji, GR ^{[1
]}

Fakhraie, SM ^{[1
]}

Smith, KC ^{[1
]}

机构：

[1] Univ Tehran, VLSI Circuits & Syst Lab, ECE Dept, Tehran, Iran

来源：

ICM 2001: 13TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, PROCEEDINGS | 2001年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a high speed and low power adder is designed using a new logic-design style called Pseudo Dynamic Logic (SDL). Traditional dynamic logic is pre-charged to a default value and in evaluate phase is changed to its real logic, However, in this logic style, the internal nodes are charged to an intermediate pre-charge value, so that the evaluation is performed faster. A 32-bit CLA adder have been designed and simulated using HSPICE Level 49 parameters of a 0.6mum CMOS process. Simulated measurements on this adder show that the worst-case delay is 1.56ns. This shows 2.1 times speed improvement and 21.2% area saving in comparison to a domino dynamic logic design implemented with the same technology.

引用

页码：137 / 140

页数：4

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