Jitter in high-speed serial and parallel links

被引：0

作者：

Hanumolu, PK ^{[1
]}

Casper, B ^{[1
]}

Mooney, R ^{[1
]}

Wei, GY ^{[1
]}

Moon, UK ^{[1
]}

机构：

[1] Oregon State Univ, Sch Elect Engn & Comp Sci, Corvallis, OR 97331 USA

来源：

2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 4, PROCEEDINGS | 2004年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Jitter degrades the performance of both high-speed serial and parallel I/O links by limiting the maximum achievable data-rates. We present analytical expressions to evaluate the effect of jitter on the performance of high-speed links. These expressions enable simple calculation of worst-case voltage and timing margins in the presence of jitter. This analysis is also extended to equalized links. Finally, we show that the limited bandwidth of the channel can amplify high frequency jitter and present means to counteract jitter amplification.

引用

页码：425 / 428

页数：4

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