Implementation of Monotonicity Testing Utilizing On Chip Resources for Test Time Reduction

Programmable System on Chip (PSoC) devices coming in to the market in recent times does possess basic elements such as configurable op-amps, counters, multiplexers, onchip capacitors, switch matrix, Advanced High-performance Bus (AHB) etc. This paper presents an implementation to test monotonic parameters of SoC utilizing available hybrid bist options and thus reducing the overhead on Automated Testing Equipment (ATE) which has accounted for Test Time Reduction (TTR). This method has been verified on one of PSoC devices at both wafer (110 units) and package (3 units) level using MAGNUM1 NEXTEST ATE and found that test time has reduced by 28.31% compared to its traditional implementation of measuring voltage for each monotonic code.