EMI reduction by chip-package-board co-design

被引：0

作者：

Kiyoshige, Sho ^{[1
]}

Ichimura, Wataru ^{[1
]}

Terasaki, Masahiro ^{[1
]}

Kobayashi, Ryota ^{[1
]}

Sudo, Toshio ^{[1
]}

机构：

[1] Shibaura Inst Technol, Koto Ku, Tokyo 108, Japan

来源：

2014 INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC EUROPE) | 2014年

关键词：

CIRCUITS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Electromagnetic radiation is always headachy issue in developing various electronic systems. Because electro-magnetic radiation and interference (EMI) is very sensitive to signal routing and physical layout of power distribution network (PDN) in package and board as well as chip design. Therefore, chip-package co-design is becoming important by taking into account the total PDN impedance seen from the chip. Especially, parallel resonance peaks in the PDN due to the chip-package interaction induces the unwanted power supply fluctuation, and results in serious EMI troubles. In this paper, three test chips were designed with different on-chip PDN properties. These three chips were intended to have typical characteristics; oscillatory region and damped condition. Then, the effects of the total PDN impedance on EMI have been studied. In particular, anti-resonance peak was properly suppressed by establishing critical damping condition in chip-package-board co-design. EMI has been proved to be dramatically reduced by proper combination of on-chip capacitance, on-chip resistance and package inductance.

引用

页码：946 / 951

页数：6

共 50 条

[41] Chip-Package-PCB Co-Design for Optimization of Wireless Receiver Performance
Sun, Ruey-Bo
Chang, Po-Yang
Wang, Ting-Kuang
Hung, Chih-Ming
[J]. 2012 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS), 2012, : 116 - 119
[42] CHIP-PACKAGE CO-DESIGN: EFFECT OF SUBSTRATE WARPAGE ON BEOL RELIABILITY
Raghavan, Sathyanarayanan
Schmadlak, Ilko
Leal, George
Sitaraman, Suresh
[J]. PROCEEDINGS OF THE ASME INTERNATIONAL MECHANICAL ENGINEERING CONGRESS AND EXPOSITION, 2013, VOL 10, 2014,
[43] Routability-Driven Bump Assignment for Chip-Package Co-Design
Chen, Meng-Ling
Tsai, Tu-Hsiung
Chen, Hung-Ming
Chen, Shi-Hao
[J]. 2014 19TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2014, : 519 - 524
[44] Flip-Chip Routing with Unified Area-I/O Pad Assignments for Package-Board Co-Design
Fang, Jia-Wei
Wong, Martin D. F.
Chang, Yao-Wen
[J]. DAC: 2009 46TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2009, : 336 - +
[45] Chip-package-board codesign of highly linear 3G-CDMA upconverter modules
Han, FY
Wu, JM
Horng, TS
Tu, CC
Chen, R
Chu, CH
[J]. 55th Electronic Components & Technology Conference, Vols 1 and 2, 2005 Proceedings, 2005, : 528 - 531
[46] System-on-chip (SoC) requires IC & package co-design and co-verification
Fontanelli, A
Arrigoni, S
Raccagni, D
Rosin, M
[J]. PROCEEDINGS OF THE IEEE 2002 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2002, : 319 - 322
[47] A Design Flow for Micro Bump and Stripe Planning on Modern Chip-Package Co-Design
Huang, Ming-Yu
Chen, Hung-Ming
Chen, Kuan-Neng
Wu, Shih-Hsien
Lee, Yu-Min
Su, An-Yu
[J]. 2020 IEEE 70TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2020), 2020, : 2236 - 2241
[48] Characterisation, modelling and design of bond-wire interconnects for chip-package co-design
Chandrasekhar, A
Stoukatch, S
Brebels, S
Balachandran, J
Beyne, E
De Raedt, W
Nauwelaers, B
Poddar, A
[J]. 33RD EUROPEAN MICROWAVE CONFERENCE, VOLS 1-3, CONFERENCE PROCEEDINGS, 2003, : 301 - 304
[49] Package-Chip Co-Design to Increase Flip-Chip C4 Reliability
Logan, Sheldon
Guthaus, Matthew R.
[J]. 2011 12TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), 2011, : 553 - 558
[50] RF Substrates Yield Improvement Using Package-Chip Co-Design and On-Chip Calibration
Goyal, Abhilash
Swaminathan, Madhavan
Chatterjee, Abhijit
[J]. 2010 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGE & SYSTEMS SYMPOSIUM, 2010,

← 1 2 3 4 5 →