Monolayer Transistor SRAMs: Toward Low-Power, Denser Memory Systems

Monolayer heterojunction FETs based on vertical heterogeneous transition metal dichalcogenides (TMD-CFETs) and planar black phosphorus FETs (BPFETs) have demonstrated excellent subthreshold swing, high ION/IOFF, and high scalability, making them attractive candidates for post-CMOS memory design. This article explores TMDCFET and BPFET SRAM design by combining atomistic self-consistent devicemodeling with SRAM circuit design and simulation. We perform detailed evaluations of the TMDCFET/BPFET SRAMs at a single bitcell and at SRAM array level. Our simulations show that at low operating voltages, TMDCFET/BPFET SRAMs exhibit significant advantages in static power, dynamic read/write noise margin, and read/write delay over nominal 16nm CMOS SRAMs at both bitcell and array-level implementations. We also analyze the effect of process variations on the performance of TMDCFET/BPFET SRAMs. Our simulations demonstrate that TMDCFET/BPFET SRAMs exhibit high tolerance to process variations, which is desirable for low operating voltages.