Product-Level Reliability Estimator with Budget-Based Reliability Management in 20nm Technology

被引：0
|
作者：
Ahn, Jae-Gyung [1 ]
Lu, Ming Peng [2 ]
Navale, Nitin [1 ]
Graves, Dawn [1 ]
Yeh, Ping-Chin [1 ]
Chang, Jonathan [1 ]
Pai, S. Y. [2 ]
机构：
[1] Xilinx Inc, FPGA Dev & Silicon Technol Grp, San Jose, CA 95124 USA
[2] Xilinx Inc, Reliabil Engn Grp, San Jose, CA 95124 USA
来源：
2015 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2015年
关键词：
product reliability; failure rate; reliability budget; TDDB; Electromigration; MOL TDDB; HTOL;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Product-level Reliability Estimator (PLRE) has been built for 20nm technology product. With PLRE, users can estimate failure rate of the chip with various use conditions. EDA tools are used to estimate each block's reliability budget, in terms of effective area for TDDB and effective number for EM which are to be used in building PLRE. Budget-based reliability check procedure was explained, which let designers have more room for reliability to get better circuit performance. Results of PLRE show that EM and MOL TDDB can be an actual risk in specific use condition.
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页数：5
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