Investigation of an advanced SiH4 based self-aligned barrier process for CuBEOL reliability performance improvement on industrial 110 nm technology

被引：4

作者：

Dumont-Girard, P ^{[1
]}

Gosset, LG ^{[1
]}

Chhun, S ^{[1
]}

Juhel, M ^{[1
]}

Girault, V ^{[1
]}

Bryce, G ^{[1
]}

Prindle, C ^{[1
]}

Torres, J ^{[1
]}

机构：

[1] STMicroelect, F-38926 Crolles, France

来源：

PROCEEDINGS OF THE IEEE 2005 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2005年

关键词：

D O I：

10.1109/IITC.2005.1499953

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper deals with the introduction of an innovative self-aligned capping layer leading to the formation of a Cu/Si/N mixed interface. The process has been first developed targeting to aggressive 65 nm technology node and below. After optimisation, the process was successfully introduced in a well known Cu/FSG integration scheme prior to SiN etch stop layer deposition; process interest and maturity was demonstrated on 3 00 mm wafers in a I 10 nm technology node by showing both its full compatibility with industrial requirements for stabilized technology and clear performance improvements in terms of electrical performances, defectivity and resistance to electro-migration. These results open large perspectives for the integration of Si-based self-aligned barrier on Cu lines, the process capability covering several technology nodes used either as in addition to thin dielectric barriers or as a single capping of the copper lines.

引用

页码：132 / 134

页数：3