Effect of gate-length downscaling on the analog/RF and linearity performance of InAs-based nanowire tunnel FET

被引:3
|
作者
Baral, Biswajit [1 ]
Biswal, Sudhansu Mohan [1 ]
De, Debashis [2 ]
Sarkar, Angsuman [3 ]
机构
[1] Silicon Inst Technol, ECE Dept, Bhubaneswar, Odisha, India
[2] West Bengal Univ Technol, CSE Dept, Kolkata, W Bengal, India
[3] Kalyani Govt Engn Coll, ECE Dept, Kolkata, W Bengal, India
关键词
III-V tunnel FET; cut-off frequency; transconductance; transconductance generation factor; gain bandwidth product; 1-dB compression point; NOISE PERFORMANCE; RF; MOSFETS; TRANSISTORS;
D O I
10.1002/jnm.2186
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, the analog/radio frequency (RF) and linearity performance of an InAs-based nanowire (NW) tunnel field-effect transistor (TFET) is studied and compared with InAs-based NW MSFET of identical dimension. InAs-based NW TFETs shows a great promise for high performance digital application because of its superior subthreshold behavior. Different analog/RF and linearity key figure-of-merits like cut-off frequency (f(t)) and 1-dB compression point are extracted and the effect of gate length down scaling on those parameters has been studied. The results reveal that down scaled InAs-based NW TFET shows a significant improvement in its RF and linearity performance. However, this advantage diminishes in terms of poor analog performance with gate-length downscaling. This clearly indicates the necessity of a trade-off between analog and RF performance. Moreover, an in-depth comparison between InAs-based NW TFET and conventional MOSFET has also been provided in order to demonstrate the superiority of InAs-based NW TFET to become a competitive contender by replacing conventional MOSFET for Analog/Mixed signal System-on-Chip (SOC) applications. Copyright (c) 2016 John Wiley & Sons, Ltd.
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页数:10
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