Study on Analog/RF and Linearity Performance of Staggered Heterojunction Gate Stack Tunnel FET

Staggered heterostructure gate stack TFET is proposed. The analog, RF, and linearity performance of the device were studied in an ATLAS TCAD device simulator. The high K material HfO2 was used in gate stacking. The impact of the gate stack width on the analog, RF, and linearity performance was investigated. Analog/RF performance of the staggered heterostructure gate stack TFET were analyzed in terms of figure of merits (FOMs) like transconductance (g(m)), transconductance generation factor (TGF), voltage gain, electric field, cut off frequency (f(T)), maximum frequency of oscillation (f(max)), and gain band width (GBW). Gate stacking architecture in heterostructure staggered TFET improves the I-on/I-off ratio and reduces drain induced barrier lowering with respect to greater gate stack width (t(oxh)), diminishing the short channel effects. Improvement in g(m) voltage gain, f(T), f(max), and GBW) were observed as the gate stack width thickened. A fair comparison of FOMs such as VIP2, VIP3, IIP3, IMD3, and 1 dB-compression point (P1 dB) were carried out by varying the gate stack width to investigate the linearity performance. The simulation results reveal that staggered heterostructure gate stack TFET can be a reasonable competitor for low-power applications and in the design of RF circuits covering a wide range in frequencies of RF spectrum.