Simulation and comparative study on analog/RF and linearity performance of III-V semiconductor-based staggered heterojunction and InAs nanowire(nw) Tunnel FET

被引：17
|
作者：
Biswal, Sudhansu Mohan [1 ]
Baral, Biswajit [1 ]
De, Debashis [2 ]
Sarkar, A. [2 ]
机构：
[1] Silicon Inst Technol, Bhubaneswar, Odisha, India
[2] MAKAUT, Kolkata, W Bengal, India
来源：
MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS | 2019年 / 25卷 / 05期
关键词：
FIELD-EFFECT TRANSISTORS; INTERMODULATION DISTORTION; GATE; MOSFET; OPTIMIZATION;
D O I：
10.1007/s00542-017-3642-z
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents the comparative study on linearity and analog/radio frequency presentation of an III-V staggered hetero-junction nanowire (NW) TFET with Si and InAs based NW TFET of same dimension. The device parameter of analog/RF performance for low power application such as transconductance (g(m)), output resistance (R-O), intrinsic gain (g(m)R(0)), cut-off frequency (f(T)), maximum frequency of oscillation (f(max)), gain bandwidth product (GBW), VIP2, VIP3 as well as 1-dB compression point has been explored. There is a better improvement in analog/radio frequency presentation obtained from heterojunction NW TFET over Si and InAs TFET. The result reveals that heterojunction TFET provides superior intrinsic gain, higher cutoff frequency, higher GBW better linearity performance as compared to Si and InAs TFET.
引用
收藏
页码：1855 / 1861
页数：7
相关论文
共 8 条
  • [1] Simulation and comparative study on analog/RF and linearity performance of III–V semiconductor-based staggered heterojunction and InAs nanowire(nw) Tunnel FET
    Sudhansu Mohan Biswal
    Biswajit Baral
    Debashis De
    A. Sarkar
    [J]. Microsystem Technologies, 2019, 25 : 1855 - 1861
  • [2] Analog/Radiofrequency and linearity performance of staggered heterojunction nanowire(nw) Tunnel FET for low power application
    Biswal, Sudhansu Mohan
    Baral, Biswajit
    De, Debashis
    [J]. PROCEEDINGS OF 2ND INTERNATIONAL CONFERENCE ON 2017 DEVICES FOR INTEGRATED CIRCUIT (DEVIC), 2017, : 441 - 445
  • [3] Study on Analog/RF and Linearity Performance of Staggered Heterojunction Gate Stack Tunnel FET
    Biswal, Sudhansu M.
    Das, Satish K.
    Misra, Sarita
    Nanda, Umakanta
    Jena, Biswajit
    [J]. ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY, 2021, 10 (07)
  • [4] Effect of gate-length downscaling on the analog/RF and linearity performance of InAs-based nanowire tunnel FET
    Baral, Biswajit
    Biswal, Sudhansu Mohan
    De, Debashis
    Sarkar, Angsuman
    [J]. INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS, 2017, 30 (3-4)
  • [5] Study of effect of gate-length downscaling on the analog/RF performance and linearity investigation of InAs-based nanowire Tunnel FET
    Biswal, Sudhansu Mohan
    Baral, Biswajit
    De, Debashis
    Sarkar, Angsuman
    [J]. SUPERLATTICES AND MICROSTRUCTURES, 2016, 91 : 319 - 330
  • [6] Simulation of III-V Material Based Steep Slope Tunnel FET for RF Harvester Application
    Selvan, Saravana
    Yik, Goh Kooh
    Ramasamy, Gobbi
    Zaman, Mukter
    [J]. INTERNATIONAL JOURNAL OF ENGINEERING AND TECHNOLOGY INNOVATION, 2019, 9 (03) : 212 - 227
  • [7] Investigation of DC, RF and Linearity Performances of III-V Semiconductor-Based Electrically Doped TFET for Mixed Signal Applications
    Rajan, Chithraja
    Samajdar, Dip Prakash
    Lodhi, Anil
    [J]. JOURNAL OF ELECTRONIC MATERIALS, 2021, 50 (04) : 2348 - 2355
  • [8] Comparative study on drive current of III-V semiconductor, Ge and Si channel n-MOSFETs based on quantum-corrected Monte Carlo simulation
    Mori, Takashi
    Azuma, Yusuke
    Tsuchiya, Hideaki
    Miyoshi, Tanroku
    [J]. IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2008, 7 (02) : 237 - 241
1