Process/physics-based threshold voltage model for nano-scaled double-gate devices

被引：20
|
作者：
Kim, K [1 ]
Fossum, JG
Chuang, CT
机构：
[1] IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA
[2] Univ Florida, Dept Elect & Comp Engn, Gainesville, FL 32611 USA
来源：
INTERNATIONAL JOURNAL OF ELECTRONICS | 2004年 / 91卷 / 03期
关键词：
D O I：
10.1080/00207210410001675653
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Compact physics/process-based model for threshold voltage in double-gate devices is presented. Predominant short-channel effects for double-gate devices, which are drain-induced barrier lowering (DIBL) and short-channel-induced barrier lowering (SCIBL), are physically analysed and modeled to be applicable to SPICE-compatible circuit simulators. The short-channel models are also developed for bulk-Si device and compared to those of double-gate devices. The validity and predictability of the models are demonstrated and confirmed by numerical device simulation results for extremely scaled L-eff = 25 nm double-gate devices and bulk-Si device.
引用
收藏
页码：139 / 148
页数：10
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