Chip on Board (COB) Versus Board on Chip (BOC) Memory Packages

被引：0

作者：

Hui, Chong Chin ^{[1
]}

Chie, Wang Ai ^{[1
]}

机构：

[1] Micron Semicond Asia Pte Ltd, Singapore 757432, Singapore

来源：

PROCEEDINGS OF THE 2013 IEEE 15TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC 2013) | 2013年

关键词：

D O I：

暂无

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Due to intense competition in the consumer electronics landscape, especially in the mobile communication products sector, new memory products (both DRAM and NAND Flash) must meet higher speed requirements, be packaged in smaller form factors, and achieve higher densities. Therefore, the most common package types-board on chip (BOC) for DRAM and chip on board (COB) for NAND Flash-must be analyzed to determine whether they can meet current and future packaging challenges. The components of COB and BOC substrates that are being studied are traces, bond fingers, the number of metal layers, and vias. Based on the trends of these substrate components, future substrates will be required to have at least two metal layers (BOC in particular), utilize narrower bond finger pitches, be thinner than 0.13mm, and have vias with via land/drill hole sizes of less than 220 mu m/100 mu m. Further work must be performed to determine the minimum required trace width value based on the existing warpage specifications as well as the minimum required bond finger pitch as a function of die length.

引用

页码：731 / 735

页数：5

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