Board Level Reliability of Wafer Level Chip Scale Packages With Copper Post Technology

被引:0
|
作者
Jacobe, April B. [1 ]
Lomibao, Pinky B. [1 ]
Jackson, John [1 ]
机构
[1] Analog Devices Inc, Gen Trias, Cavite, Philippines
关键词
D O I
暂无
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Thermal cycling performance of wafer level chip scale packages (WLCSP) depends on many factors: board design, assembly process and bump processes. The typical failure mode observed for this package is fracture between die and solder bump interface, To strengthen the base of the solder ball during thermal cycling, electroplated copper post was embedded on the RDL, and is encapsulated in a low stress molding compound. The post increases the standoff which is believed to have better reliability. Time-to-failure, plotted in a Weibull distribution will be used to illustrate interesting and significant differences.
引用
收藏
页码:155 / 161
页数:7
相关论文
共 50 条
  • [1] Reliability of Wafer Level Chip Scale Packages
    Rongen, R.
    Roucou, R.
    vd Wel, P. J.
    Voogt, F.
    Swartjes, F.
    Weide-Zaage, K.
    [J]. MICROELECTRONICS RELIABILITY, 2014, 54 (9-10) : 1988 - 1994
  • [2] Board level reliability of chip scale packages
    Wang, ZP
    Tan, YM
    Chua, KM
    [J]. 1998 INTERNATIONAL SYMPOSIUM ON MICROELECTRONICS, 1998, 3582 : 513 - 518
  • [3] Board level reliability of chip scale packages
    Hung, SC
    Zheng, PJ
    Chen, HN
    Lee, SC
    Lee, JJ
    [J]. 1999 INTERNATIONAL SYMPOSIUM ON MICROELECTRONICS, PROCEEDINGS, 1999, 3906 : 571 - 580
  • [4] Investigations of board-level drop reliability of wafer-level chip-scale packages
    Lai, Yi-Shao
    Yeh, Chang-Lin
    Wang, Ching-Chun
    [J]. JOURNAL OF ELECTRONIC PACKAGING, 2007, 129 (01) : 105 - 108
  • [5] Board level reliability assessment of chip scale packages
    Wang, ZP
    Tan, YM
    Chua, KM
    [J]. MICROELECTRONICS RELIABILITY, 1999, 39 (09) : 1351 - 1356
  • [6] Drop test reliability of wafer level chip scale packages
    Alajoki, M
    Nguyen, L
    Kivilahti, J
    [J]. 55TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, VOLS 1 AND 2, 2005 PROCEEDINGS, 2005, : 637 - 644
  • [7] Structural design optimization for board-level drop reliability of wafer-level chip-scale packages
    Tsai, Tsung-Yueh
    Lai, Yi-Shao
    Yeh, Chang-Lin
    Chen, Rong-Sheng
    [J]. MICROELECTRONICS RELIABILITY, 2008, 48 (05) : 757 - 762
  • [8] Optimal design towards enhancement of board-level thermomechanical reliability of wafer-level chip-scale packages
    Lai, Yi-Shao
    Wang, Tong Hong
    [J]. MICROELECTRONICS RELIABILITY, 2007, 47 (01) : 104 - 110
  • [9] Cyclic bending reliability of wafer-level chip-scale packages
    Lai, Yi-Shao
    Wang, Tong Hong
    Tsai, Han-Hui
    Jen, Ming-Hwa R.
    [J]. MICROELECTRONICS RELIABILITY, 2007, 47 (01) : 111 - 117
  • [10] Study on Board Level Drop Reliability of Wafer Level Chip Scale Package with Leadfree Solder
    Zhang Xueren
    Zhu Wenhui
    Edith, Poh
    Boon, Tan Hien
    [J]. EPTC: 2008 10TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, VOLS 1-3, 2008, : 1096 - 1101