Board Level Reliability of Wafer Level Chip Scale Packages With Copper Post Technology

被引：0
|
作者：
Jacobe, April B. [1 ]
Lomibao, Pinky B. [1 ]
Jackson, John [1 ]
机构：
[1] Analog Devices Inc, Gen Trias, Cavite, Philippines
来源：
IEMT 2006: 31ST INTERNATIONAL CONFERENCE ON ELECTRONICS MANUFACTURING AND TECHNOLOGY | 2006年
关键词：
D O I：
暂无
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
Thermal cycling performance of wafer level chip scale packages (WLCSP) depends on many factors: board design, assembly process and bump processes. The typical failure mode observed for this package is fracture between die and solder bump interface, To strengthen the base of the solder ball during thermal cycling, electroplated copper post was embedded on the RDL, and is encapsulated in a low stress molding compound. The post increases the standoff which is believed to have better reliability. Time-to-failure, plotted in a Weibull distribution will be used to illustrate interesting and significant differences.
引用
收藏
页码：155 / 161
页数：7
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