An Edge Missing Compensator for Fast Settling Wide Locking Range Phase-Locked Loops

被引：14

作者：

Lin, Chi-Sheng ^{[1
]}

Chien, Ting-Hsu ^{[1
]}

Wey, Chin-Long ^{[1
,2
]}

Huang, Chun-Ming ^{[1
]}

Juang, Ying-Zong ^{[1
]}

机构：

[1] Natl Chip Implementat Ctr, Natl Appl Res Labs, Hsinchu, Taiwan

[2] Natl Cent Univ, Dept Elect Engn, Jhongli, Taiwan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2009年 / 44卷 / 11期

关键词：

Edge missing comparator; edge missing detector; extended linear region; phase-locked loop (PLL); FREQUENCY-SYNTHESIZER;

D O I：

10.1109/JSSC.2009.2031209

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An edge missing compensator (EMC) is proposed to approach the function of an ideal PD with +/- 2(N-1) X 2 pi linear range with N-bit EMC. A PLL implemented with a 9-bit EMC achieves 320 MHz frequency hopping within 10 mu s logarithmically which is about 2.4 times faster than the conventional design. The reference spur of the PLL is -48.7 dBc and the phase noise is -88.31 dBc/Hz at 10 kHz offset with K-VCO = -2 GHz/V.

引用

页码：3102 / 3110

页数：9

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