Time-Mode Techniques for Fast-Locking Phase-Locked Loops

A fast-locking phase-locked loop (PLL) with variable loop dynamics is proposed. The PLL employs a time amplifier (TA) with a variable gain to amplify the phase difference between the reference clock and the output of the voltage controlled oscillator (VCO). It operates by dynamically increasing the bandwidth of the PLL during locking state to speed up locking process and decreasing the bandwidth of the PLL in locked state to optimize the performance of the PLL. The insertion of the TA also reduces the time constant of the loop filter without sacrificing performance, thereby allowing the reduction of the resistance and capacitance of the loop filter subsequently their silicon and power consumption. The increased width of Up and Down pulses also enable the reduction of the current of the charge pump while achieving the same variation of the control voltage thereby lowering the power consumption. Two identical PLLs, one with the TA and the other without were designed in an IBM 0.13 mu m CMOS 1.2 V technology and analyzed using SpectreRF from Cadence Design Systems with BSIM4 device models. Both critically damped and under-damped cases were investigated. Simulation results demonstrate that in the critically damped case, the lock time of the PLL with the TA is 0.42 mu s while that without is 0.52 mu s. In the under damped case, the lock time of the PLL with the TA is 0.30 mu s while that without is 1.54 mu s.