A Lightweight Posit Processing Unit for RISC-V Processors in Deep Neural Network Applications

被引:16
|
作者
Cococcioni, Marco [1 ]
Rossi, Federico [1 ]
Ruffaldi, Emanuele [2 ]
Saponara, Sergio [1 ]
机构
[1] Univ Pisa, Dept Informat Engn, I-56122 Pisa, Italy
[2] MMI SpA, I-56011 Calci, Italy
基金
欧盟地平线“2020”;
关键词
Alternative representations of real numbers; posit arithmetic; hardware synthesis; RISC-V processors; instruction set architecture extension; scalar operations;
D O I
10.1109/TETC.2021.3120538
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Nowadays, two groundbreaking factors are emerging in neural networks. First, there is the RISC-V open instruction set architecture (ISA) that allows a seamless implementation of custom instruction sets. Second, there are several novel formats for real number arithmetic. In this work, we combined these two key aspects using the very promising posit format, developing a light Posit Processing Unit (PPU-light). We present an extension of the base RISC-V ISA that allows the conversion between 8 or 16-bit posits and 32-bit IEEE Floats or fixed point formats in order to offer a compressed representation of real numbers with little-to-none accuracy degradation. Then we elaborate on the hardware and software toolchain integration of our PPU-light inside the Ariane RISC-V core and its toolchain, showing how little it impacts in terms of circuit complexity and power consumption. Indeed, only 0.36% of the circuit is devoted to the PPU-light while the full RISC-V core occupies the 33% of the overall circuit complexity. Finally we present the impact of our PPU-light on a deep neural network task, reporting speedups up to 10 on sample inference processing time.
引用
收藏
页码:1898 / 1908
页数:11
相关论文
共 50 条
  • [1] Faster deep neural network image processing by using vectorized posit operations on a RISC-V processor
    Cococcioni, Marco
    Rossi, Federico
    Ruffaldi, Emanuele
    Saponara, Sergio
    REAL-TIME IMAGE PROCESSING AND DEEP LEARNING 2021, 2021, 11736
  • [2] RISC-V Barrel Processor for Deep Neural Network Acceleration
    AskariHemmat, MohammadHossein
    Bilaniuk, Olexa
    Wagner, Sean
    Savaria, Yvon
    David, Jean-Pierre
    2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2021,
  • [3] Vectorizing posit operations on RISC-V for faster deep neural networks: experiments and comparison with ARM SVE
    Marco Cococcioni
    Federico Rossi
    Emanuele Ruffaldi
    Sergio Saponara
    Neural Computing and Applications, 2021, 33 : 10575 - 10585
  • [4] Vectorizing posit operations on RISC-V for faster deep neural networks: experiments and comparison with ARM SVE
    Cococcioni, Marco
    Rossi, Federico
    Ruffaldi, Emanuele
    Saponara, Sergio
    NEURAL COMPUTING & APPLICATIONS, 2021, 33 (16): : 10575 - 10585
  • [5] PERI: A Configurable Posit Enabled RISC-V Core
    Tiwari, Sugandha
    Gala, Neel
    Rebeiro, Chester
    Kamakoti, V
    ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 2021, 18 (03)
  • [6] Rapid RISC: Fast Customization of RISC-V Processors
    Donofrio, David D.
    Leidel, John D.
    OPEN ARCHITECTURE/OPEN BUSINESS MODEL NET-CENTRIC SYSTEMS AND DEFENSE TRANSFORMATION 2022, 2022, 12119
  • [7] On-Board Decision Making in Space with Deep Neural Networks and RISC-V Vector Processors
    Di Mascio, Stefano
    Menicucci, Alessandra
    Gill, Eberhard
    Furano, Gianluca
    Monteleone, Claudio
    JOURNAL OF AEROSPACE INFORMATION SYSTEMS, 2021, 18 (08): : 553 - 570
  • [8] RISC-V Extension for Lightweight Cryptography
    Tehrani, Etienne
    Graba, Tarik
    Merabet, Abdelmalek Si
    Danger, Jean-Luc
    2020 23RD EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2020), 2020, : 222 - 228
  • [9] A lightweight ISE for ChaCha on RISC-V
    Marshall, Ben
    Page, Daniel
    Thinh Hung Pham
    2021 IEEE 32ND INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP 2021), 2021, : 25 - 32
  • [10] Design of a Generic Security Interface for RISC-V Processors and its Applications
    Oh, Hyunyoung
    Park, Junmo
    Yang, Myonghoon
    Hwang, Dongil
    Paek, Yunheung
    2018 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2018, : 40 - 41