Yield Improvement of 3D ICs in the Presence of Defects in Through Signal Vias

被引：0

作者：

Nain, Rajeev K. ^{[1
]}

Pinge, Shantesh ^{[1
]}

Chrzanowska-Jeske, Malgorzata ^{[1
]}

机构：

[1] Portland State Univ, Dept Elect & Comp Engn, Portland, OR 97207 USA

来源：

PROCEEDINGS OF THE ELEVENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2010) | 2010年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Through signal vias (TSVs) in 3D ICs suffer from thermo-mechanical stress, and may fail or attain plasticity resulting in significant yield loss. We present a novel set of strategies for yield improvement in the presence of defects in through signal vias in heterogeneous 3D system-on-chip. Monte-Carlo simulation results show that our strategy can improve the yield of 3D ICs significantly. Furthermore, we estimate the parametric yield and present a quantitative analysis of the impact of our approach on chip area, power, performance and chip revenue that can improve profitability. Our results suggest that the proposed strategies can be very useful in yield-aware 3D design.

引用

页码：598 / 605

页数：8

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