Supply voltage strategies for minimizing the power of CMOS processors

被引：6

作者：

Cai, J ^{[1
]}

Taur, Y ^{[1
]}

Huang, SF ^{[1
]}

Frank, DJ ^{[1
]}

Kosonocky, S ^{[1
]}

Dennard, RH ^{[1
]}

机构：

[1] IBM Corp, TJ Watson Res Ctr, Yorktown Hts, NY 10598 USA

来源：

2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2002年

关键词：

D O I：

10.1109/VLSIT.2002.1015408

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a dual supply voltage strategy for reduction of the total (static and dynamic) power of high performance CMOS processors. By expressing CMOS delay, static power. and dynamic power in terms of the power supply voltage V-DD and threshold voltage V-T, an optimization procedure that takes the circuit activity factor into account is performed to find the VDD and VT for minimum total power at given performance levels. It is shown that 50% power reduction or 20% performance enhancement can be attained by adopting both a low (0.5V) supply voltage for high-activity circuits and a high (1.2V) supply voltage for low-activity circuits in a 100 nm-node CMOS technology.

引用

页码：102 / 103

页数：2

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