Wafer Level 3D Stacking using Smart Cut™ and Metal-Metal Direct Bonding Technology

被引：3

作者：

Di Cioccio, L. ^{[1
]}

Radu, I.

Baudin, F. ^{[1
]}

Mounier, A. ^{[1
]}

Lacave, T. ^{[1
]}

Delaye, V. ^{[1
]}

Imbert, B. ^{[1
]}

Chevalier, N. ^{[1
]}

Mariolle, D. ^{[1
]}

Thieffry, S. ^{[2
]}

Mazen, F. ^{[1
]}

Gaudin, G. ^{[2
]}

Signamarcheix, T. ^{[1
]}

机构：

[1] CEA Grenoble, LETI, MINATEC Campus,17 Rue Martyrs, F-38054 Grenoble 9, France

[2] SOITEC, Parc Technol Fontaines, F-38926 Crolles, France

来源：

SEMICONDUCTOR WAFER BONDING 12: SCIENCE, TECHNOLOGY, AND APPLICATIONS | 2012年 / 50卷 / 07期

关键词：

SILICON-ON-INSULATOR;

D O I：

10.1149/05007.0169ecst

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

While significant research effort on various planar approaches, the 3D vertical IC stacking is undoubtedly gaining increasing momentum as a leading contender in the challenge to meet performance, cost, and size demands through this decade and beyond. The Smart Cut (TM) technology allowing the stack of very thin layers with direct bonding is one of the emerging technologies in this field. In this paper, the Smart Cut (TM) technology using low temperature metal direct bonding (allowing direct vertical integration) is demonstrated.

引用

页码：169 / 175

页数：7

共 50 条

[21] 3D Technology based on aligned wafer-to-wafer direct bonding for capacitive coupling interconnectivity.
Charlet, B
Di Cioccio, L
Dechamp, J
Zussy, M
Enot, T
Canegallo, R
Fazzi, A
Guerrieri, R
Advanced Metallization Conference 2005 (AMC 2005), 2006, : 173 - 177
[22] Wafer Level Embedding Technology for 3D Wafer Level Embedded Package
Kumar, Aditya
Xia Dingwei
Sekhar, Vasarla Nagendra
Lim, Sharon
Keng, Chin
Sharma, Gaurav
Rao, Vempati Srinivas
Kripesh, Vaidyanathan
Lau, John H.
Kwong, Dim-Lee
2009 IEEE 59TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, VOLS 1-4, 2009, : 1289 - +
[23] 3D CMOS-MEMS Stacking with TSV-less and Face-to-Face Direct Metal Bonding
Chua, S. L.
Razzaq, A.
Wee, K. H.
Li, K. H.
Yu, H.
Tan, C. S.
2014 SYMPOSIUM ON VLSI TECHNOLOGY (VLSI-TECHNOLOGY): DIGEST OF TECHNICAL PAPERS, 2014,
[24] Bonding Technologies for Chip Level and Wafer Level 3D integration
Sakuma, Katsuyuki
Skordas, Spyridon
Zitzi, Jeffrey
Perfecto, Eric
Guthrie, William
Guerin, Luc
Langlois, Richard
Liu, Hsichang
Ramachandran, Koushik
Lin, Wei
Winste, Kevin
Kohara, Sayuri
Sueoka, Kuniaki
Angyal, Matthew
Graves-Abel, Troy
Berger, Daniel
Knickerbocker, John
Iyer, Subramanian
2014 IEEE 64TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2014, : 647 - 654
[25] Adhesion Property of Polyimide and Passivation Layer for Polymer/metal Wafer-level Hybrid Bonding in 3D Integration
Lu, Cheng-Hsien
Kho, Yi-Tung
Yang, Yu-Tao
Chen, Yu-Pei
Chen, Chiao-Pei
Hung, Tsung-Tai
Chen, Chiu-Feng
Chen, Kuan-Neng
2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2018), 2018, : 401 - 406
[26] Low Temperature Wafer Bonding for Wafer-Level 3D Integration
Dragoi, V.
Rebhan, B.
Burggraf, J.
Razek, N.
2014 4TH IEEE INTERNATIONAL WORKSHOP ON LOW TEMPERATURE BONDING FOR 3D INTEGRATION (LTB-3D), 2014, : 9 - 9
[27] Reliability Assessment of 3D Chip Stacking Package Using Metal Bonding and Through Silicon Via Technologies
Syu, Shih-Yi
Hung, Tuan-Yu
Huang, Chao-Jen
Wang, Han-Jung
Lee, Hsin-Li
Chiang, Kuo-Ning
PROCEEDINGS OF THE ASME INTERNATIONAL MECHANICAL ENGINEERING CONGRESS AND EXPOSITION 2010, VOL 4, 2012, : 125 - +
[28] Wafer-level direct bonding of optimized superconducting NbN for 3D chip integration
Li, Ye
Gheytaghi, Amir Mirza
Trifunovic, Miki
Xu, Yuanxing
Zhang, Guo Qi
Ishihara, Ryoichi
PHYSICA C-SUPERCONDUCTIVITY AND ITS APPLICATIONS, 2021, 582
[29] 3D interconnect through aligned wafer level bonding
Lindner, P
Dragoi, V
Glinsner, T
Schaefer, C
Islam, R
52ND ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2002 PROCEEDINGS, 2002, : 1439 - 1443
[30] Chip-to-wafer stacking technology for 3D system integration
Klumpp, A
Merkel, R
Wieland, R
Ramm, P
53RD ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2003 PROCEEDINGS, 2003, : 1080 - 1083

← 1 2 3 4 5 →