Wafer Level 3D Stacking using Smart Cut™ and Metal-Metal Direct Bonding Technology

被引：3

作者：

Di Cioccio, L. ^{[1
]}

Radu, I.

Baudin, F. ^{[1
]}

Mounier, A. ^{[1
]}

Lacave, T. ^{[1
]}

Delaye, V. ^{[1
]}

Imbert, B. ^{[1
]}

Chevalier, N. ^{[1
]}

Mariolle, D. ^{[1
]}

Thieffry, S. ^{[2
]}

Mazen, F. ^{[1
]}

Gaudin, G. ^{[2
]}

Signamarcheix, T. ^{[1
]}

机构：

[1] CEA Grenoble, LETI, MINATEC Campus,17 Rue Martyrs, F-38054 Grenoble 9, France

[2] SOITEC, Parc Technol Fontaines, F-38926 Crolles, France

来源：

SEMICONDUCTOR WAFER BONDING 12: SCIENCE, TECHNOLOGY, AND APPLICATIONS | 2012年 / 50卷 / 07期

关键词：

SILICON-ON-INSULATOR;

D O I：

10.1149/05007.0169ecst

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

While significant research effort on various planar approaches, the 3D vertical IC stacking is undoubtedly gaining increasing momentum as a leading contender in the challenge to meet performance, cost, and size demands through this decade and beyond. The Smart Cut (TM) technology allowing the stack of very thin layers with direct bonding is one of the emerging technologies in this field. In this paper, the Smart Cut (TM) technology using low temperature metal direct bonding (allowing direct vertical integration) is demonstrated.

引用

页码：169 / 175

页数：7

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