共 50 条
- [41] A self-biased high performance folded cascode CMOS op-amp [J]. TENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 1997, : 429 - 434
- [42] Slew-Rate Enhancement for a Low-Power Two Stage CMOS OP-AMP in Nanometer Regime [J]. JOURNAL OF ACTIVE AND PASSIVE ELECTRONIC DEVICES, 2016, 11 (04): : 313 - 321
- [43] A Low Power Miller Compensation Technique for Two Stage Op-amp in 65nm CMOS Technology [J]. 2019 10TH INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION AND NETWORKING TECHNOLOGIES (ICCCNT), 2019,
- [44] Ultra high gain CMOS Op-Amp design using self-cascoding and positive feedback [J]. MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS, 2017, 23 (03): : 541 - 552
- [45] Voltage Buffer Compensation using Flipped Voltage Follower in a Two-Stage CMOS Op-amp [J]. 2015 IEEE 58TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2015,
- [46] An efficient design of CMOS comparator and folded cascode op-amp circuits using particle swarm optimization with an aging leader and challengers algorithm [J]. International Journal of Machine Learning and Cybernetics, 2016, 7 : 325 - 344
- [48] Ultra high gain CMOS Op-Amp design using self-cascoding and positive feedback [J]. Microsystem Technologies, 2017, 23 : 541 - 552
- [49] Design Automation of CMOS Op-Amps Using Statistical Geometric Programming [J]. 2022 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 22), 2022, : 1575 - 1579
- [50] PHONO PRE-AMP USING FERRANTI ZN 424 OP-AMP [J]. ELECTRONIC ENGINEERING, 1979, 51 (632): : 19 - 19