A Low Power Miller Compensation Technique for Two Stage Op-amp in 65nm CMOS Technology

A critical review of the Miller compensation technique for a two-stage operational amplifier (op-amp) is presented in this paper. The trade-offs involved in the compensation capacitor value and the small signal parameters of the op-amp are also considered in this paper; that is, the second stage requires a higher bias current, while driving a large capacitive load for a given phase-margin. A technique is presented with a view to increase the g(m) of the second stage without increasing the power dissipation, hence improving the phase margin while maintaining the unity gain bandwidth (UGB) of the op-amp. A prototype has been designed in 65nm CMOS technology and post-layout simulations exhibit good performance characteristics of 45MHz UGB with 250fF compensation capacitor, for a supply voltage of 1.2V, and a current consumption of 132 mu A. The new technique shows a superior performance to those obtained with an established compensation technique that achieves a 10MHz UGB while dissipating the same power. The total circuit size is 0.00234mm2 silicon area.