Design and analysis of Two stage op-amp in 180nm CMOS Process

被引：0

作者：

Smrithi, V. ^{[1
]}

Sam, D. S. Shylu ^{[1
]}

Manoj, G. ^{[1
]}

机构：

[1] Karunya Inst Technol & Sci, Dept Elect & Commun Engn, Coimbatore, India

来源：

2024 7TH INTERNATIONAL CONFERENCE ON DEVICES, CIRCUITS AND SYSTEMS, ICDCS 2024 | 2024年

关键词：

CMOS; op-amp; gain; slew rate; cadence; HIGH-SPEED; AMPLIFIER; OPTIMIZATION;

D O I：

10.1109/ICDCS59278.2024.10560977

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Operational amplifiers are an integral part of an electronic system. Typical uses of the operational amplifier are amplifiers, oscillators, filters and also used in many types of instrumentation circuits. Two stage CMOS opamp is widely accepted due to its simplicity in design topology and its robustness. The design of op-amps continues to pose a challenge as the supply voltage and transistor channel lengths scale down with each generation of CMOS technologies. Operational amplifier is very high gain differential amplifier with high input impedance and low output impedance. Simulation results shows that the power dissipation, Gain and CMRR of the proposed op-amp is 1.3mW, 60dB and 48.7dB in 180 nm CMOS Process.

引用

页码：253 / 257

页数：5

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